1. Field of the Invention
The present invention relates generally to data communication systems, and more particularly but not exclusively to phase and frequency detection circuits.
2. Description of the Background Art
In serial data communication systems, data bit streams are transmitted using a certain voltage waveform (e.g. NRZ (non-return to zero) waveform) via transmission lines to remote receivers. To reduce cost, a typical data communication system does not employ dedicated transmission lines to carry clock or timing information. In such a communication system, a remote receiver needs to extract the clock from the incoming data bit stream. Phase-locked-loops (PLLs) are often used in serial data receivers to extract clocks embedded in incoming data bit streams. A typical PLL consists of a phase/frequency detector, a loop filter, and a voltage-controlled oscillator (VCO). The VCO is used to generate a local clock, referred to as “VCO clock”. The phase/frequency detector detects the phase and frequency differences between the VCO clock and the clock embedded in the incoming data bit stream. The phase and frequency differences are filtered by the loop filter and are used to control the frequency and consequently the phase of the VCO clock. The clock embedded in the incoming bit stream is thus recovered in a closed-loop manner by the PLL.
A phase detector (PD) is a key component of a PLL used for clock and data recovery. The phase detector enables the PLL to properly align the phase of the VCO clock with that of the incoming bit stream, so that the receiver can sample the incoming data bit stream at a proper timing instant, preferably at the midpoint of each bit interval. Linear phase detectors and binary phase detectors are two types of phase detectors normally used for clock and data recovery. An example linear phase detector is disclosed in U.S. Pat. No. 4,535,459. A linear phase detector generates a pulse representing the phase error between incoming data and VCO clock. The pulse width is proportional to the phase error. A problem with linear phase detectors is that they may not work well at very high-speed data rates because the detector has to generate a very narrow pulse for a small phase error. Unbalanced loading and delay mismatch can worsen this problem. Therefore, linear phase detectors suffer from a relatively large phase error. In a very high-speed link, a slight misalignment can lead to a significant increase of bit error rate.
A binary phase detector generates a pulse of fixed width, which usually covers one data bit interval, of a polarity indicating whether the incoming data or the VCO clock is leading in phase. A binary phase detector is also known as “bang-bang” because of its phase detection characteristic as shown in FIG. 1. A binary phase detector generates an output signal VOUT that is either positive or negative depending on the phase relationship between the incoming data and VCO clock. For example, the binary phase detector may be configured to generate a positive output signal VOut when the VCO clock is lagging the incoming data, and a negative output signal VOut when the VCO clock is leading the incoming data.
A phase detector by itself cannot capture the incoming data if the initial frequency of the VCO clock differs too much from the baud rate of the incoming data (“data baud rate”). In that case, a frequency detector (FD) has to be added into the loop to aid data acquisition. Commonly used frequency detectors can be classified into two categories: quadricorrelator frequency detectors and rotational frequency detectors. A quadricorrelator is well known for its analog implementations, which require many special analog components, such as rectifiers, differentiator, etc. These analog components are very sensitive to process, voltage, and temperature variations. If not carefully designed, a system employing a quadricorrelator may not function as expected.
In contrast to quadricorrelator frequency detectors, rotational frequency detectors are implemented using digital circuits. Rotational frequency detectors are disclosed in the following two papers: “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gigabit/s” by A. Pottbacker et al. in IEEE Journal of Solid State Circuits, December, 1992, pp 1747–1751 and “Frequency Detectors for PLL Acquisition In Timing and Carrier Recovery” by D. G. Messerschmitt in IEEE Trans. on Communications, September 1979, pp 1288–1295.
FIG. 2 shows a block diagram of a conventional PLL system 200 utilizing a phase and frequency detector. The PLL system 200 consists of a rotational frequency detector 222, a phase detector (PD) 206, a summer 208, a charge pump (CP) circuit 209, a low pass filter (LPF) 210, and a VCO 211. The rotational frequency detector 222 consists of an in-phase detector (IPD) 201, a quadrature-phase detector (QPD) 202, a frequency detector (FD) 203, and a summer 204. The rotational frequency detector 222 also includes a lock-in detector (LID) 207 used to detect whether the PLL system 200 has successfully locked in the frequency of the clock embedded in the incoming data (simply labeled as “DATA” in FIG. 2). When the frequency of the embedded clock is not yet locked, the LID 207 controls a tri-state buffer 205 to enable the rotational frequency detector output 226 to control the VCO 211 via the summer 208, the CP 209, and the LPF 210. When the frequency of the incoming data is locked in within a certain range, the LID 207 controls the tri-state buffer 205 to disable the rotational frequency detector output 226. In that case, the VCO 211 is solely controlled by the PD output 228. The PD output 228 represents the phase error between the in-phase clock CLK_I and the incoming data stream.
The VCO 211 generates an in-phase clock CLK_I and a quadrature-phase clock CLK_Q, which are 90 degrees out of phase with each other. As is conventional, the incoming data is used to sample both the in-phase clock CLK_I and the quadrature-phase clock CLK_Q by the in-phase detector 201 and by the quadrature-phase detector 202, respectively. Both IPD 201 and QPD 202 are binary phase detectors and compare the phase relationship between incoming data and their respective VCO clock. Their outputs are provided to the FD 203 to detect the frequency error. The IPD output 220 and the FD output 225 are combined by the summer 204, resulting in the output 226. When there is a frequency difference between the clock embedded in the incoming data and the VCO clock, the rotational frequency detector output 226 comprises pulses of exclusively the same polarity that depends on whether the VCO clock is faster or slower. In practice, however, due to circuit non-idealities and mismatches between the IPD output 220 and the FD output 225, the rotational frequency detector output 226 won't have the same polarity even when there is a frequency error. This degrades the performance of the PLL system 200. Furthermore, the output of the rotational frequency detector 222 needs to be disabled by the LID 207 when the VCO frequency has been locked to within a certain range, otherwise the rotational frequency detector 222 may disrupt phase locking. Unfortunately, the LID 207 may falsely detect an out-of-lock condition and improperly enable the rotational frequency detector output 226. This causes further PLL performance degradation.